招生需求：

歡迎有誌於模擬/射頻及數模混合集成電路研究與設計🧜🏽‍♀️、勇於創新的碩士、博士研究生及博士後加入。

實驗室提供開放的科研環境🧥，與工業界接軌的項目和實習機會📗。

研究方向💆🏽‍♀️：

1.模擬及射頻集成電路設計🦯，包括收發機(Transceiver)及時鐘(PLL)電路設計

2.高速接口電路（SerDes）設計

3.模數/數模轉換器(ADC/DAC)設計

教育背景：

2008年09月-2013年03月美國俄勒岡州立大學，電子與計算機工程，博士

2005年09月-2008年06月沐鸣娱乐◻️👮🏽，微電子學👨‍👩‍👧，碩士

2001年09月-2005年07月沐鸣娱乐，微電子學🤦🏽‍♀️，學士

工作經歷：

2020年11月-至今沐鸣娱乐👨🏻‍🎨🍞，研究員，博士生導師
2013年04月-2020年10月三星半導體（美國），高級工程師、主任工程師🎩、高級主任工程師

代表性論文👨🏼‍💼、著作及專利🎼：

1.J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, J. Chang, S. Kang, K. Son, H. Lim, D. Jeong, I. Jong, S. Baek, J. Lee, R. Ni, Y. Zuo, C. Yao, S. Heo, T. Cho, and I. Kang, “A sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.54, no.12, pp.3541-3552, 2019;

2.W. Wu, C.W. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, “A 28-nm 75-fs(rms) Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.54, no.5, pp.1254-1265, 2019;

3.J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, S. Ahn, S. Kang, Q. Bui, K. Son, H. Lim, D. Jeong, R. Ni, Y. Zuo, I. Jong, C. Yao, S. Heo, T. Cho, and I. Kang, “A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS”, IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), vol.62, pp.354-356, 2019;

4.W. Wu, C. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, “A 5.5-7.3 GHz analog fractional-N sampling PLL in 28-nm CMOS with 75 fsrmsJitter and -249.7 dB FoM”, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol.2018-June, pp.52-55, 2018;

5.S. Ko, C. Yao, J. Lee, S. Han, D. Kwon, W. Loke, R.Ni, and T. Cho, “Digital PLL design challenges for cellular RFICs”, IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), pp.232-234, 2017;

6.C. Yao, R. Ni, C. Lau, W. Wu, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, “A 14-nm 0.14-ps(rms) Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.52, no.12, pp. 3446-3457, 2017;

7.C. Yao, W. Loke, R. Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, “A 14nm Fractional-N Digital PLL with 0.14ps(rms) Jitter and-78dBc Fractional Spur for Cellular RFICs”, IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), vol.60, pp.422-422, 2017;

8.R. Ni, K. Mayaram, and T. Fiez, “A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with-76dBm sensitivity for high data rate wireless sensor networks”, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (VLSI), 2014;

9.R. Ni, K. Mayaram, and T. Fiez, “A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.48, no.5, pp.1250-1263, 2013;

10.R. Ni, K. Mayaram, and T. Fiez, “A 2.4GHz Hybrid PPF Based BFSK Receiver with +/-180ppm Frequency Offset Tolerance for Wireless Sensor Networks”, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (VLSI), pp.40-41, 2012;

11.R. Ni, “Low Power Receivers for Wireless Sensor Networks”, Ph.D. Dissertation, Oregon State University, 2013;

12.C. Yao, R. Ni, “System and Method for Fast-Converging Digital-to-Time Converter (DTC) Gain Calibration for DTC-based Analog Fractional-N Phase Lock Loop (PLL)”, U.S. Patent, US 2019/0212703 A1;