專用集成電路與系統國家重點實驗室
講座信息：Automated Design Analysis and Merging
for Speeding up FPGA Development

報告人🔷：Professor Wayne Luk（英國帝國理工）
時間👰🏻：2018年5月28日上午9:30-11:30
地點👨‍🍼：張江校區微電子樓269室

Abstract🐼：
This talk introduces an approach for merging multiple FPGA designs into a single hardware design, so that multiple place and-route tasks can be replaced by a single task to speed up functional evaluation of designs, especially during the development process. The proposed approach has three key elements. First, a novel approximate maximum common subgraph detection algorithm with linear time complexity to maximize sharing of resources in the merged design. Second, a prototype tool implementing this common subgraph detection algorithm for dataflow graphs derived from Verilog designs; this tool would also generate the appropriate control circuits to enable selection of the original designs at runtime. Third, a comprehensive analysis of compilation time versus degree of similarity to identify the optimized user parameters for the proposed approach. Experimental results show that this approach can reduce compilation time by around 5 times when each design is 95% similar to the others, and the compilation time is reduced from 1 hour to 10 minutes in the case of binomial filters.

 
Biography🤲🏻：
Wayne Luk is Professor of Computer Engineering at Imperial College London. His research covers the development of hardware and software capabilities to address demanding applications, such as genomic data processing and climate modelling. He is a fellow of the Royal Academy of Engineering, the IEEE and the BCS. He is a recipient of the Research Excellence Award from Imperial College London, and 15 awards for his publications from various international conferences.

聯系人🛴🏋️‍♂️：王伶俐